Timing Analysis Engineer Jobs

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Staff Physical Design Engineer, HBM

Micron Technology Inc Richardson, TX

Richardson, TX

Today

Full time Senior Design Design Engineering

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Job Description

Micron’s HBM Digital Design organization is seeking a Staff Physical Design Engineer to lead backend implementation from synthesized netlist through GDSII for advanced memory products. In this onsite role in Richardson, TX, you will help deliver high-performance, low-power digital logic by driving timing closure, improving power integrity, and ensuring manufacturability. You will collaborate across RTL, DFT, CAD, and verification teams to move designs from concept to signoff.

What you’ll do

Own end-to-end physical design execution from synthesized netlist to GDSII, including floorplanning, placement, clock tree synthesis, routing, and physical signoff
Use AI-Enabled tools in the Netlist to GDS flow
Drive timing closure across multiple modes, corners, and scenarios using industry-standard STA tools
Analyze and resolve issues impacting quality of results, including congestion, timing, IR drop, EM, and power integrity
Develop and refine floorplans, power grids, and clocking strategies for high-performance designs
Partner with placement and timing closure for custom analog hard IP macros in a digital-on-top design flow
Collaborate with RTL designers early to influence partitioning, constraints, and micro-architecture decisions
Implement and validate low-power design techniques, including multiple/isolated power domains, power gating, and UPF/CPF power intent
Execute physical verification coverage including DRC/LVS/ANT/DFM and support signoff flows
Drive functional and timing ECOs as needed to hit design targets
Improve productivity and flow robustness using scripting and automation (TCL, Python, etc.)
Work with EDA vendors and internal CAD teams to debug tool issues, evaluate new tools, and enhance physical design methodologies

What you bring

Strong understanding of the RTL-to-GDSII physical design flow, including floorplanning, place & route, clock distribution, and timing analysis/closure using standard EDA tools and advanced process technologies
Experience with full-chip integration, partitioning, and budgeting
Solid understanding of power, performance, and area tradeoffs
Knowledge of low-power architectures, including DVFS, power gating, and multi-voltage designs
Proficiency in scripting/programming: TCL, Python, Perl, Shell scripting
Strong problem-solving skills and ability to debug complex physical design issues
Effective communication skills and ability to work in a cross-functional team environment
Experience validating Power Distribution Network (PDN), IR/EM

Technology areas

GDSII, UPF, CPF
STA, TCL, Python, Perl, Shell scripting
DVFS, DRC, LVS, ANT, DFM
AI-Enabled tools, IR/EM, Power Distribution Network (PDN)

Benefits

Choice of medical, dental, and vision plans
Benefit programs that help protect your income if you are unable to work due to illness or injury
Paid family leave
Robust paid time-off program and paid holidays

Education and experience

Required: Bachelor’s degree in EE with good understanding of computer architecture and 7+ years experience in related field
Desired: Master’s degree in EE / CE with 5+ years experience in related field

Preferred qualifications

Experience with advanced technology nodes
Experience with high-frequency, high-density designs and complex clocking schemes
Familiarity with memory, HBM, or datapath-intensive designs
Understanding of device physics and process-technology impacts
Experience with 3D-IC technology, methodology, and advanced packaging and thermal considerations

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