Clock Optimization Engineer Jobs

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Today

EDA/CAD Software Engineer, Staff

Qualcomm San Diego, CA

San Diego, CA

Today

$146k - $218k/yr Full time Electrical Engineering Manager Asic Design

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Job Description

Qualcomm is hiring a Staff-level EDA/CAD Software Engineer to help build and improve critical CAD tooling used in emulation for Qualcomm SoC needs. In this role, you will work with industry-standard technologies to develop emulation-focused CAD algorithms and contribute to compute and storage optimization while mentoring and leading team members. The position sits within Qualcomm Technologies Inc’s Global CAD team, which develops tools, flows, and methodologies across VLSI design.

What you’ll do

Partner with industry-standard tools and technologies to deliver solutions for a range of infrastructure needs.
Develop emulation CAD algorithms tailored to unique Qualcomm SoC requirements, including synthesis, partitioning, place and route, and clock optimization.
Drive compute and storage optimization efforts.
Mentor and lead other members of the team.

Required qualifications

Education: PhD in Science, Engineering, or related field.
Minimum 2+ years ASIC design, FPGA design, verification, or related work experience.
Minimum 2+ years C++ software development, CAD tool development, or related experience.
Minimum 2+ years of hands-on experience with Linux.
Minimum 2+ years of direct hands-on experience with CAD software development, including demonstrated software design principles, practices, and patterns.
Demonstratable knowledge of data structures, algorithms, and design patterns.
Experience with RTL Synthesis (System Verilog to netlist), Clock Tree Optimization, and exposure to VLSI design concepts, including logic design.
Excellent interpersonal and analytical skills, with the ability to work independently and build customer-facing applications.
Experience with Git, LSF, JIRA, GCC, and related technologies.
Experience alternatives (as listed): A required combination of degree and years of related ASIC design/verification/validation/integration work may qualify based on a Bachelor’s (4+ years), Master’s (3+ years), or PhD (2+ years) pathway.
Experience baseline: Minimum 2 years of related work experience.

Technologies you may work with

C++, Linux, Git, LSF, JIRA, GCC
System Verilog, RTL Synthesis
Clock Tree Optimization
ASIC design, FPGA design, emulation
Place and route, partitioning, clock optimization

Location and compensation

Location: San Diego, CA (onsite)

Pay range: USD 145,600 - 218,400 per year

Benefits

Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package

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