Asic Design

Asic Design Engineer Jobs

2 jobs found

Today

Sr Principal ASIC FPGA Engineer

General Dynamics Mission Systems, Inc Scottsdale, AZ

Scottsdale, AZ

Today

$182k - $202k/yr Full time Electrical Engineering Senior Asic Design

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Job Description

General Dynamics Mission Systems, Inc is hiring a Senior Principal ASIC FPGA Engineer for the Space Systems Engineering team in Scottsdale, Arizona (hybrid). In this role, you will own ASIC/FPGA definition, design, verification, and documentation, including architecture, simulation, device design, and process flow evaluation.

Key Responsibilities

Own ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) definition, design, verification, and documentation
Determine architecture, system simulation approach, and detailed design direction
Define module interfaces and support all aspects of device design and simulation
Evaluate process flow, including high level design, synthesis, place and route, timing, and power utilization
Create test and simulation plans with functional criteria and verify outcomes through analysis of performance
Review vendor capabilities, foundry technologies, device libraries, and simulation tools as needed
Apply expert knowledge of organizationally defined processes across the program or project lifecycle
Contribute to development, maintenance, and improvement of ASIC/FPGA organizational processes
Generate technical engineering products by using applicable standards, processes, procedures, and tools throughout the development life cycle
Lead research and analysis using customer design proposals, specifications, and manuals to determine feasibility
Select components and equipment based on specification review and reliability analysis
May contribute to technical subcontract management for medium to large subcontracts, including SOW development, proposal evaluation, source selection, technical oversight, and subcontractor work product evaluation and acceptance
Support large or complex proposals, including establishing the overall ASIC/FPGA technical approach and participating in integrated product teams or working groups
May supervise or manage lower level employees and serve in roles such as Deputy Program Manager Engineering (DPME)
Work on advanced applications that may support new business opportunities
Exercise latitude in setting technical objectives and work under consultative direction on predetermined long-range objectives
Identify opportunities to apply AI for continuous improvement and innovation

Required Qualifications

Bachelor’s degree in Electrical or Computer Engineering (or related Science, Engineering, or Mathematics field) with a minimum of 10 years of relevant experience; or a Master’s degree with a minimum of 8 years of relevant experience
Demonstrated use and understanding of ASIC/FPGA engineering concepts, principles, and theories
Demonstrated understanding of company policies and practices and of ASIC/FPGA engineering processes
Demonstrated awareness of business objectives and Engineering’s role in achieving them
Proficiency in Microsoft Office applications
Demonstrated written and verbal communications skills
Ability to think creatively and multi-task
Ability to communicate issues, impacts, and corrective actions
Ability to recognize and clearly report information relevant to sound engineering design
Ability to apply project leadership principles, including SPI/CPI, Earned Value, Cost Account Management (CAM), and Statistical Process Controls
Demonstrated ability to manage scope growth and maintain frequent contact across the organization
Ability to serve as a consultant to management and customers and, when needed, as a company technical spokesperson
Ability to work under consultative direction on long-range objectives, with assignments that may be self-initiated
Experience with unusually complex problems and delivery of creative, innovative solutions
Ability to identify and pursue AI opportunities for continuous improvement and innovation

Preferred Clearance and Citizenship

Department of Defense TS/SCI security clearance is preferred at time of hire
Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire
Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information
Due to the nature of work performed within company facilities, U.S. citizenship is required

Technology and Tools

Microsoft Office
SPI/CPI
Earned Value
Cost Account Management (CAM)
Statistical Process Controls

Location and Work Model

Scottsdale, AZ
Hybrid (role can be remote, flex, or onsite)
Onsite team member base: Scottsdale, AZ location
#LI-Hybrid
#CJ1

Benefits

Flexible schedules with every other Friday off work, if desired (9/80 schedule)
Competitive benefits, including 401k matching
Flex time off
Paid parental leave
Healthcare benefits
Health and wellness programs
Employee resource and social groups

Additional Commitment

Research oriented work with award winning teams focused on practical solutions for national security
Career path with opportunities for continuous learning and development
See more at gdmissionsystems.com/careers/why-work-for-us/benefits

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Today

EDA/CAD Software Engineer, Staff

Qualcomm San Diego, CA

San Diego, CA

Today

$146k - $218k/yr Full time Electrical Engineering Manager Asic Design

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Job Description

Qualcomm is hiring a Staff-level EDA/CAD Software Engineer to help build and improve critical CAD tooling used in emulation for Qualcomm SoC needs. In this role, you will work with industry-standard technologies to develop emulation-focused CAD algorithms and contribute to compute and storage optimization while mentoring and leading team members. The position sits within Qualcomm Technologies Inc’s Global CAD team, which develops tools, flows, and methodologies across VLSI design.

What you’ll do

Partner with industry-standard tools and technologies to deliver solutions for a range of infrastructure needs.
Develop emulation CAD algorithms tailored to unique Qualcomm SoC requirements, including synthesis, partitioning, place and route, and clock optimization.
Drive compute and storage optimization efforts.
Mentor and lead other members of the team.

Required qualifications

Education: PhD in Science, Engineering, or related field.
Minimum 2+ years ASIC design, FPGA design, verification, or related work experience.
Minimum 2+ years C++ software development, CAD tool development, or related experience.
Minimum 2+ years of hands-on experience with Linux.
Minimum 2+ years of direct hands-on experience with CAD software development, including demonstrated software design principles, practices, and patterns.
Demonstratable knowledge of data structures, algorithms, and design patterns.
Experience with RTL Synthesis (System Verilog to netlist), Clock Tree Optimization, and exposure to VLSI design concepts, including logic design.
Excellent interpersonal and analytical skills, with the ability to work independently and build customer-facing applications.
Experience with Git, LSF, JIRA, GCC, and related technologies.
Experience alternatives (as listed): A required combination of degree and years of related ASIC design/verification/validation/integration work may qualify based on a Bachelor’s (4+ years), Master’s (3+ years), or PhD (2+ years) pathway.
Experience baseline: Minimum 2 years of related work experience.

Technologies you may work with

C++, Linux, Git, LSF, JIRA, GCC
System Verilog, RTL Synthesis
Clock Tree Optimization
ASIC design, FPGA design, emulation
Place and route, partitioning, clock optimization

Location and compensation

Location: San Diego, CA (onsite)

Pay range: USD 145,600 - 218,400 per year

Benefits

Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package

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Asic Design Engineer Jobs

Sr Principal ASIC FPGA Engineer

EDA/CAD Software Engineer, Staff

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