Staff DRAM Design Engineer

Micron Technology Inc is seeking a Staff DRAM Design Engineer to help advance next-generation memory by shaping DRAM circuit and memory architecture decisions from early concept through silicon validation. Based in Boise, ID, this onsite role focuses on simulation-driven design, layout-aware optimization, and clear validation planning in close collaboration with cross-functional teams.

Role Overview

In this position, you will design and optimize DRAM circuits and memory architectures, using circuit simulation and architectural analysis to guide trade-offs across power, performance, and die size. You will also integrate layout parasitics into simulations and steer designs toward manufacturability. A key part of the work is defining validation strategies, including test chip development and silicon bring-up.

Responsibilities

• Lead design and optimization of DRAM circuits, covering the memory array, control logic, datapath, and test logic
• Perform and analyze circuit simulations using tools such as SPICE and Verilog
• Evaluate architectural trade-offs that affect power, performance, and die size
• Integrate layout parasitics into simulations and drive design choices for manufacturability
• Define validation strategies, including test chip development and silicon bring-up

Requirements

• Bachelor’s degree in Electrical Engineering or a related field
• 5+ years of circuit design experience or 7+ years of product engineering experience
• Strong understanding of analog and digital circuit fundamentals and debugging
• Experience with circuit simulation tools and methodologies
• Knowledge of CMOS behavior, timing, and performance optimization

Technology Stack

• SPICE
• Verilog

Benefits

• Choice of medical, dental, and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

Preferred Qualifications

• Experience with memory architectures, especially DRAM array design and sense amplifiers
• Familiarity with DFT/DFM concepts and semiconductor test flows
• Experience working with layout parasitics and advanced process nodes
• Ability to communicate complex technical concepts clearly across teams
• Interest or experience in applying AI tools to engineering workflows

Location: Boise, ID (onsite)

Minimum Experience: 5 years

Title: Staff DRAM Design Engineer

Education: Bachelor’s degree in Electrical Engineering or related field