Analog Layout Engineer

Capgemini is hiring an experienced Analog / RF Layout Engineer for an onsite role supporting advanced semiconductor nodes and analog and mixed-signal IP development.

Responsibilities

• Independently create block-level and IP-level analog/RF layouts, collaborating with circuit designers and global layout teams to drive designs from concept through tape-out
• Own floorplanning, placement, routing, and optimization for complex analog and mixed-signal blocks, including SerDes, ADC/DACs, PLLs, and related IP
• Lead and support top-level integration of multiple analog and mixed-signal blocks within larger SoCs
• Apply deep expertise in advanced deep sub-micron and FinFET process technologies, incorporating fabrication, EM, ESD, latch-up, and reliability considerations into layouts
• Resolve complex DRC, LVS, antenna, and other verification-related layout issues using strong technical judgment
• Collaborate across geographies and support technical leadership by mentoring or guiding team members

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics, or a related field
• 6+ years of hands-on analog and/or RF layout design experience (8+ years preferred)
• Proven experience in analog floor planning and layout for complex modules such as SerDes, ADC/DAC, PLLs, and similar high-speed or precision circuits
• Strong understanding of analog layout best practices for deep sub-micron CMOS and FinFET technologies

Benefits

• Paid time off based on employee grade (A-F): Vacation 12-25 days depending on grade, plus Company paid holidays, Personal Days, and Sick Leave
• Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
• Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
• Life and disability insurance
• Employee assistance programs
• Other benefits as provided by local policy and eligibility

Location and Compensation

• Location: Onsite in San Francisco, CA (noted as onsite in Santa Clara, CA)
• Salary: USD 97,700 - 203,800 per year