Hardware Security Engineer

The Hardware Security Engineer role on the HW-CSDL team at Cisco Systems is focused on translating hardware security evaluation outcomes into implementable design guidance. This position serves as a technical security advisor to hardware engineering teams to help achieve HW-CSDL compliance and align designs with global security regulations.

Role Overview

As part of the Security& Trust Organization, the engineer bridges security assessment findings and practical hardware design requirements. The position supports product hardware teams by identifying vulnerabilities across hardware architectures and helping teams design in resilience from the system level down to boards and components.

Responsibilities

• Partner with product hardware teams to review results from hardware security evaluations and provide actionable, clear, and pragmatic design guidance for HW-CSDL compliance.
• Deconstruct and assess complex hardware architectures across the system stack, including boards, ASICs/FPGAs, power/management controllers, and discrete components to identify vulnerabilities and strengthen design resilience.
• Parse, interpret, and operationalize emerging industry and government standards (including NIST SP 800-193, CNSA 2.0, EU Cyber Resilience Act, and IEEE 2883) into technical guidance and design requirements.
• Author high-quality security guidelines, reference architectures, implementation guides, and best-practice documentation for engineering audiences across Cisco.
• Participate in, lead, and coordinate multiple parallel engagements, consulting efforts, and security initiatives across diverse product families.
• Educate and influence hardware design communities outside STO to support a security-first culture across the product development lifecycle.

Required Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field with 7+ years of relevant hardware design or engineering experience, or a Master’s degree with 4+ years of experience.
• Background in hardware development, including reading and interpreting system-level schematics, block diagrams, component datasheets, PCB design or review, or register-level hardware documentation.
• Background in hardware security fundamentals, including Hardware Root of Trust (RoT), Secure Boot, hardware and firmware resiliency, cryptographic primitives (symmetric/asymmetric encryption, hashing, digital signatures), and secure key storage.

Technologies and Tools

• NIST SP 800-193, CNSA 2.0, EU Cyber Resilience Act, IEEE 2883
• Hardware Root of Trust (RoT), Secure Boot
• Cryptographic primitives (symmetric/asymmetric encryption, hashing, digital signatures)
• TCG DICE / TPM, OCP Secure Boot
• Fault injection, side-channel analysis, JTAG/debug security
• Python, Bash, Verilog, SystemVerilog
• LLM-assisted compliance checks, automated review scripts, security analysis tooling

Team and Customer Focus

The Security& Trust Organization (S) holds corporate-level responsibility for customer data protection and compliance, corporate information protection, and government and product security. Security is highlighted as a key concern for Cisco customers and a major investment area.

Benefits

• Health insurance (medical, dental and vision)
• 401(k) plan with a Cisco matching contribution
• Paid parental leave
• Short and long-term disability coverage
• Basic life insurance
• Restricted stock units (RSUs) eligibility (vesting following continued employment with Cisco for defined periods of time)
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for an employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees: 16 days of paid vacation time per full calendar year (accrued at 4.92 hours per pay period for full-time employees)
• Exempt employees: participate in Cisco’s flexible vacation time off program (no defined limit)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, with up to 80 hours of unused sick time carried forward
• Optional 10 paid days per full calendar year to volunteer
• Annual bonuses for non-sales roles (subject to Cisco’s policies)
• Performance-based incentive pay on top of base salary for employees on sales plans (subject to Cisco’s policies)

Location and Employment Type

Research Triangle Park, NC (hybrid).

Compensation

Salary range: USD 132,800 - 259,100 per yearly.

The starting salary range posted for U.S. and/or Canada locations is $132,800.00 to $185,100.00 and reflects the projected salary range for new hires in this position, excluding incentive compensation, equity, or benefits. Individual pay is determined by hiring location, market conditions, and job-related factors including skillset, experience, qualifications, education, and training.

Applicable full salary ranges by state:

• New York City Metro Area: $154,900.00 - $259,100.00
• Non-Metro New York state & Washington state: $136,500.00 - $228,300.00

Application Deadline

The application window is expected to close on 11/29/2026.

Meet the Application Profile

• Experienced hardware engineer with a background in hardware design, low-level architecture, and security principles.
• Comfort translating sophisticated technical standards into practical engineering requirements and partnering across teams to address complex hardware security problems.
• Ability to communicate technical concepts clearly through engineering documentation and cross-functional collaboration while managing multiple parallel technical initiatives in a dynamic environment.

Preferred Qualifications

• Experience with AI-assisted development and automation for hardware security applications (including LLM-assisted compliance checks, automated review scripts, or security analysis tooling).
• Experience with scripting (Python, Bash) and RTL design or verification (Verilog, SystemVerilog) for hardware security solutions development.
• Background in hardware security frameworks and standards such as NIST SP 800-193, NSA CNSA 2.0, TCG DICE / TPM, OCP Secure Boot, IEEE 2883, and global cybersecurity regulations (for example, EU CRA).
• Experience with hardware threat modeling or hardware security analysis, including fault injection, side-channel analysis, and JTAG/debug security.
• Experience participating in hardware security industry forums, working groups, or standards bodies.