Senior Digital Design Engineer

General Dynamics Mission Systems, Inc. is seeking a Senior Digital Design Engineer in Scottsdale, AZ to research, design, develop, and test electronic equipment and systems for defense and intelligence missions. This role includes technical leadership, mentoring, and hands-on work designing and routing multi-layer printed circuit boards.

Role Overview

In this position, you will contribute to the development of integrated electronic solutions, including the design and validation of multi-layer PCBs with controlled impedance layers and blind micro-vias. You will also stay aligned with evolving industry and departmental trends to help ensure delivery consistent with, and/or exceeding, industry best practices.

Responsibilities

• Apply creative thinking and ideation to advance business performance.
• Deliver innovative, flexible, integrated solutions to support changing customer business needs.
• Support and engage in programs, projects, and practices connected to GDMS culture and strategy, and comply with all policies and procedures.
• Monitor industry and department developments to align GDMS services with industry best practices.
• Provide technical leadership and/or direction to lower level designers.

Required Qualifications

• Bachelor’s degree in Electrical Engineering, or a related Science, Engineering, Technology or Mathematics field.
• 5+ years of job-related experience, or a Master's degree plus 3 years of job-related experience.
• Department of Defense TS/SCI security clearance is preferred at time of hire.
• Ability to obtain a TS/SCI clearance within a reasonable amount of time from date of hire.
• U.S. Government security investigation eligibility and meeting requirements for access to classified information.
• U.S. citizenship is required due to the nature of work performed within GDMS facilities.

Experience and Technical Skills

• Experience with schematic capture.
• Extensive experience designing multi-layer printed circuit boards with controlled impedance layers and blind micro-vias.
• Ability to analyze and test for signal integrity and crosstalk.
• Familiarity with several families of microprocessors, microcontrollers, FPGAs, and System-on-Chips.
• Demonstrated initiative on assignments with strong independent judgment.
• Ability to technically lead and mentor less senior engineers.

Preferred Experience

• Experience with Allegro and/or Mentor design tools.
• High Reliability or Space experience.
• Experience with Worst Case Analysis and Stress Analysis.
• Ability to identify opportunities to apply AI for continuous improvement and innovation.

Tools and Technologies

Allegro and/or Mentor design tools, microprocessors, microcontrollers, FPGAs, System-on-Chips, Worst Case Analysis, Stress Analysis.

Work Location and Workplace Options

The position is onsite in Scottsdale, AZ. Workplace options are listed as fully on-site, or Hybrid/Flex as desired.

Compensation

USD 118,519 to 131,482 per year. Combined Salary Range: USD $118,519.00 - USD $131,482.00 /Yr.

Benefits

• Flexible schedules with every other Friday off work if desired (9/80 schedule).
• Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, and employee resource and social groups.

Security and Posting Details

• Department of Defense TS/SCI security clearance is preferred at time of hire.
• Candidates must be able to obtain TS/SCI within a reasonable amount of time from date of hire.
• Selected applicants will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information.
• U.S. citizenship is required due to work performed within GDMS facilities.
• This job posting will remain open until the position is filled.