Graphics Design Verification Engineer

Graphics Design Verification Engineer role focusing on pre-silicon RTL verification for low power embedded graphics cores within Apple SoC/GPU design efforts.

Responsibilities

• Own top-level verification for logic blocks in GPU designs
• Write, run, and track progress against test plans
• Build testbench components in SystemVerilog and UVM, including checkers and monitors
• Create top-level tests to validate chip-level features
• Enable, maintain, and support regressions
• Write and maintain test benches and BFMs
• Generate stimulus and implement/analyze coverage
• Debug simulation and silicon GPU failures
• Partner with design and micro-architecture teams to align on functional goals
• Coordinate verification across DV scopes with multi-functional teams
• Develop scripts for software engineering flows

Requirements

• BS + 3 years of relevant experience
• Knowledge of CPU or GPU architectures
• Experience with Verilog or other HDLs
• Verification language experience: SystemVerilog/UVM/OVM
• Experience using HDL simulation tools and waveform viewers: IES, VCS, DVE, Verdi

Technologies

• System Verilog
• Universal Verification Methodology (UVM)
• OVM
• Verilog
• IES
• VCS
• DVE
• Verdi
• Perl
• Shell scripting
• Makefiles
• TCL
• Perforce

Preferred Qualifications

• Experience working with GPU architectures
• Understanding of constrained random verification, functional/code coverage, and assertion methodology
• Experience developing UVM testbench components, including checkers and monitors
• Familiarity with Perl, Shell scripting, Makefiles, TCL
• Exposure to code repositories such as Perforce
• Ability to collaborate effectively with teams across verification efforts

Location: Austin, TX (onsite)

Employment type: Not specified