Graphics Design Verification Engineer

The Graphics Design Verification Engineer will spearhead pre-silicon RTL verification for logic blocks inside low power embedded graphics cores as part of Apple’s GPU design efforts. This onsite role in Austin focuses on building and running UVM/SystemVerilog verification environments, coordinating execution and tracking, and resolving simulation and silicon issues.

Responsibilities

• Lead top-level verification teams for logic blocks within graphics processing unit (GPU) designs.
• Own the overall development, execution, and tracking of the team’s test plans.
• Architect test bench methodology using Universal Verification Methodology (UVM) and SystemVerilog components.
• Build verification stimulus, define coverage strategy, and develop regression plans.
• Own and maintain test benches and bus functional models (BFMs).
• Debug simulation and silicon GPU failures, including complex design and environmental issues.
• Coordinate verification efforts through discussions with design and micro-architecture teams, and with other cross-functional teams.
• Generate and present weekly status updates to the GPU leadership team.

Requirements

• BS + 10 years of relevant experience.
• Background in CPU or GPU architectures.
• Experience working with Verilog or other HDLs.
• Experience architecting test benches with SystemVerilog and UVM/OVM.
• Experience with constrained random verification, functional and code coverage, and assertion methodology.
• Experience debugging complex design and environmental issues.

Preferred Qualifications

• Ability to manage multiple priorities under strict schedule deadlines.
• Expertise in GPU architectures.
• Experience with HDL simulators and waveform viewers including IES, VCS, DVE, and Verdi.
• Experience with Perl, Shell scripting, Makefiles, and TCL.
• Ability to work well on teams with experience collaborating across technical disciplines.

Required Education

BS

Location and Work Mode

Austin, TX (onsite)

Skills and Tools

• Universal Verification Methodology (UVM), System Verilog, Verilog, OVM
• IES, VCS, DVE, Verdi
• IES, VCS, DVE, Verdi (waveform viewing and simulation)
• Perl, Shell scripting, Makefiles, TCL