Senior Principal ASIC FPGA Engineer

This hands-on technical leadership role provides end-to-end ownership from architecture through silicon for advanced-node ASIC/FPGA designs, with a primary focus on RTL correctness, verification closure, and timing sign-off. The position requires independent leadership across planning, foundry and process considerations, and full tape-out execution.

Key Responsibilities

• Own the architecture by defining the ASIC/FPGA technical approach from concept through silicon, including system partitioning, microarchitecture, and interface definition
• Lead detailed RTL development with emphasis on correctness, including bus fabric integrity, clock domain crossings, and reset order-of-operations, along with design-for-verification practices
• Drive timing closure by guiding synthesis, place and route, and static timing analysis, with a focus on resolving timing issues in advanced process nodes
• Lead verification activities as the primary point of contact, developing and owning test and simulation plans with rigorous functional criteria, and driving closure on verification failures
• Own JIRA triage for the team by reviewing incoming issues, prioritizing work items, and ensuring the backlog reflects program reality
• Conduct and lead RTL code reviews, establishing the technical bar and providing actionable feedback to engineers at multiple levels
• Support program planning through contributions to Integrated Master Schedule (IMS) development and Earned Value (EV) reporting, providing technical input on task status, completion criteria, and schedule risk
• Evaluate process flows from high-level design through GDSII, including synthesis, P&R, timing, power analysis, and DFT considerations
• Guide technology selection by assessing foundry technologies, device libraries, IP cores, and EDA tooling to inform design decisions
• Support proposals and subcontracts by leading ASIC/FPGA technical approach on large proposals; serve as book boss on medium proposals; manage technical subcontracts including SOW development, source selection, and work product acceptance
• Grow the team by mentoring junior and mid-level engineers and contributing to improvements in organizational ASIC/FPGA design processes
• Collaborate broadly through participation in multi-divisional or multi-company Integrated Product Teams and working groups

Required Qualifications

• Bachelor’s degree in Electrical or Computer Engineering (or related Science, Engineering or Mathematics field) with a minimum of 10 years of relevant experience; or a Master’s degree with a minimum of 8 years of relevant experience
• Ability to obtain a Department of Defense Secret security clearance at time of hire
• Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information
• U.S. citizenship required due to the nature of work performed within company facilities
• 10–15+ years of ASIC/FPGA design experience, with the majority as an RTL designer rather than a purely backend or physical design role
• Proven experience taking designs through full ASIC tape-out, including timing closure, physical verification, and post-silicon bring-up
• Deep familiarity with FinFET process nodes (7nm, 5nm, or similar), including an understanding of FinFET vs. planar technology nuances
• Experience with commercial foundry flows, including TSMC, GlobalFoundries, Samsung, or equivalent
• Expert-level understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows
• Strong familiarity with industry-standard EDA tools across synthesis, simulation, formal verification, and STA
• Demonstrated ability to operate independently by identifying problems, driving resolution, and maintaining momentum without day-to-day direction
• Ability to evaluate vendor and foundry capabilities to support product development decisions
• Track record of innovative technical contributions that shape the approach, not only execution to specification
• Solid understanding of organizational processes, with practical application across program lifecycle elements such as schedule management and earned value inputs
• Proficiency in JIRA for issue tracking and backlog management
• Proficiency in Microsoft Office for documentation and communication

Technologies and Tools

• JIRA
• Microsoft Office
• Integrated Master Schedule (IMS)
• Earned Value (EV)
• GDSII
• EDA tools: synthesis, simulation, formal verification, STA
• TSMC, GlobalFoundries, Samsung
• FinFET

Location and Employment Details

• Location: Boise, ID (hybrid)
• Salary range: USD 191,146 to 212,053 per year
• Minimum experience: 10 years