Sr. Physical Design Engineer - Static Timing Analysis, Cloud Scale Machine Learning

Annapurna Labs (U.S.) Inc. seeks a Senior Physical Design STA Engineer to join the Cloud-Scale Machine Learning Acceleration team in Cupertino, onsite. The role centers on hardware design optimization for data centers, with a focus on static timing analysis, timing constraints, and automation, through close collaboration with RTL and architecture teams. Salary is USD 183,000 to 247,600 per year.

Responsibilities

• Develop and maintain flows for block-level and full-chip static timing analysis
• Write, debug, and validate timing constraints for blocks and the complete chip
• Execute Static Timing Analysis and provide regular feedback to team members and leads
• Offer guidance on resolving timing issues, including generating ECOs and addressing constraint problems
• Develop scripts to automate timing analysis workflows and produce reports
• Contribute as a collaborative member of a startup-like team, coordinating with other physical design engineers as well as RTL and architecture groups

Requirements

• Experience with scripting languages such as Perl, Python, or JavaScript
• Education: BS with 8+ years, MS with 6+ years, or PhD with 4+ years in EE or CS
• Strong foundation in timing analysis fundamentals
• 3+ years of hands-on experience performing Static Timing Analysis
• 3+ years of experience developing timing constraints
• Experience with timing analysis using EDA tools (examples: PrimeTime, Tempus, or equivalents)
• Understanding of ASIC Physical Design from RTL to GDSII
• Familiarity with other sign-off activities (IR/EM, physical verification, DFT)

Technologies

• Perl
• Python
• JavaScript
• PrimeTime
• Tempus
• PT-DMSA
• Tempus-ECO
• Tweaker
• STAR-RC
• Quantus
• SPICE
• SPECTRE
• DDR
• HBM
• PCIe
• Die-to-Die

Benefits

• Health insurance
• 401(k) matching
• Paid time off
• Parental leave
• Sign-on payments
• Restricted stock units (RSUs)