Principal Foundry Interface Design Engineer, HBM

Micron Technology Inc is seeking a Principal Foundry Interface Design Engineer to help align foundry process capabilities with scalable, high-performance architecture for advanced HBM DRAM products. This onsite role in Richardson, TX focuses on bridging Micron design organizations, foundry partners, and technology development teams, while advancing AI-enabled workflows to improve engineering productivity, decision quality, and execution efficiency.

The position supports technology evaluation, design enablement, and silicon learning through simulation, compact and PDK model assessment, test chip planning, and post-silicon correlation. With a salary range of USD 150,000 to 308,000 per year, the role is well suited for experienced engineers who can drive technical closure across the DTCO and foundry interface lifecycle.

Responsibilities

• Serve as the primary technical interface between foundry partners and Micron design organizations.
• Drive closure of design-process gaps by collaborating with foundry process teams.
• Influence foundry roadmaps covering TSV, BEOL, reliability, and design enablement.
• Define technology requirements for future HBM and custom memory products.
• Run HSPICE simulations to evaluate technology and optimize design.
• Evaluate compact models, PDK SPICE models, and process corners.
• Perform pre-layout and post-layout circuit analysis, including BEOL optimization and routing studies through simulation.
• Develop methodologies for evaluating design sensitivity to process variations.
• Plan and implement technology evaluation test chips.
• Define process monitor structures and benchmark vehicles.
• Analyze post-silicon data and correlate results with simulations.
• Collaborate with product engineering and foundry/Fab teams on silicon learning and technology qualification.
• Evaluate foundry PDKs and IP collateral.
• Provide technology guidelines and best-known methods to support design teams.
• Drive creation of design recommendations, analog guidelines, and digital PPA evaluation methodologies.
• Collaborate with CAD teams on flow enablement and validation.
• Identify and implement AI-enabled workflows, automation opportunities, and knowledge-management practices across DTCO, foundry interface, PDK evaluation, and design enablement.

Requirements

• BS, MS, or PhD (or equivalent experience) in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of semiconductor industry experience and strong understanding of advanced semiconductor technology development.
• Strong grasp of advanced CMOS technology nodes, FinFET devices, and process integration.
• Hands-on experience with HSPICE simulations, Device characterization, Standard cell benchmarking, PPA analysis, Parasitic extraction, and physical verification.
• Experience driving AI-enabled engineering practices and automation to improve DTCO analysis efficiency, foundry collateral evaluation, PDK enablement, benchmarking, and collaboration across build teams.

Preferred Qualifications

• Experience working directly with leading foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries.
• Experience with memory products including DRAM, HBM, or SRAM.
• Knowledge of TSV technologies, Advanced packaging, Reliability modeling and aging simulations, Advanced BEOL technologies, and PDK development and validation.
• Ability to apply AI tools to summarize, analyze, and extract insights from PDK documentation, Design Rule Manuals (DRMs), reliability reports, foundry collateral, and silicon characterization data.
• Experience leading technology pathfinding and node selection activities.

Technologies

• HSPICE
• PDK SPICE models