Sr. Principal Metrology Engineer

Diamond Foundry is seeking a Sr. Principal Metrology Engineer to lead metrology efforts for single-crystal diamond materials and devices. The role focuses on advancing characterization techniques, strengthening quality and process control, and building automated data analysis workflows in close partnership with R&D, process engineering, and manufacturing.

Key Responsibilities

• Develop, validate, and optimize metrology techniques for single-crystal diamond materials and devices, with emphasis on surface, structural, and wafer-level characterization.
• Create and improve metrology recipes to support precision wafer measurements across process flows, and provide support for thermal characterization activities.
• Define metrology protocols for critical backend processes including singulation, polishing, thinning, cleaning, and bonding.
• Implement statistical process control (SPC) and support compliance with industry standards.
• Collaborate with R&D and process engineering to correlate metrology results with process variations, perform failure analysis, and optimize process flows.
• Work with manufacturing teams to integrate metrology solutions into production workflows, troubleshoot measurement-related challenges, and interface with equipment vendors.
• Build automated data analysis pipelines to improve the efficiency and accuracy of measurement reporting.

Required Qualifications

• PhD or MS in Physics, Materials Science, Electrical Engineering, or a related field.
• Experience requirements: 5+ years (PhD) or 8+ years (MS) in semiconductor, advanced materials, metrology, or failure analysis.
• Experience with advanced characterization tools and methods including AFM, WLI, AOI, SEM, and wafer characterization, including tool qualification, calibration, and maintenance.
• Experience with statistical data analysis, SPC, and software tools such as JMP, Python, or MATLAB.
• Thermal and electrical characterization experience (examples include TDTR, FDTR, LFA, EBD) is a plus.
• Familiarity with semiconductor backend processes (examples include CMP, dicing, bonding) is highly desirable.
• Strong communication and problem-solving skills, with the ability to operate in a fast-paced, cross-functional environment.

Relevant Technologies

• AFM, WLI, AOI, SEM
• TDTR, FDTR, LFA, EBD
• JMP, Python, MATLAB
• SPC
• CMP, dicing

Location and Work Model

San Francisco Bay Area, CA (onsite).

Compensation

USD 140,000 - 195,000 per year.

Benefits

• Company shares (position is eligible for company shares)
• Health insurance
• Flexible spending accounts
• Retirement savings plans
• Life and disability insurance programs
• Programs that provide for both paid and unpaid time away from work
• Employee discounts to VRAI
• Medical and vision coverage (retroactive to start date)
• Dental and voluntary benefits (take effect once enrollment is completed)

Physical Requirements

• Use appropriate PPE and follow all safety policies, practices, and procedures.
• Often involves sitting, standing for long periods, walking, grasping, reaching with hands and arms, lifting below and above shoulders, bending, twisting at the waist, climbing, balance, stooping, squatting, kneeling, crawling, talking, hearing, seeing, using fine finger manipulation, and completing repetitive motions.
• Some tasks may require the use of ladders or stairs.
• Some tasks may require driving or the use of foot controls.
• Lift/carry and push/pull up to 50 pounds.