Principal PCB & Substrate Layout Engineer

Responsibilities

• Lead the design, layout, and analysis of intricate electrical and mechanical systems, including high-density interposers, substrates, and multi-layer PCBs, handling power, digital, analog, and RF signals across multiple dies with a primary emphasis on flip-chip configurations.
• Perform hands-on work on high-speed, multi-layer packaging and HDI interconnects, including blind and buried vias, BGAs, RF sections, design for test, impedance calculations, crosstalk, differential pairs, stack-ups, vias, EMC, and material studies/selection.
• Ensure designs follow supplier design-for-manufacturing rules and align processes with supplier capabilities.
• Prepare fabrication drawings that reflect design intent and support seamless transfer to fabrication suppliers.
• Support package material characterization with frequency-dependent models, including skin effects, surface finish, roughness, dielectric loss, and dielectric constant.
• Collaborate with peers to review artwork and drawings at various stages and participate in final design reviews for fabrication and assembly.
• Support multidisciplinary investigations and feasibility studies across engineering disciplines.
• Provide technical guidance interfacing with customers, subcontractors, assemblers, fabricators, vendors, operations, quality, supply chain, and supporting organizations.
• Tackle complex issues that require in-depth analysis of variable factors and apply systems thinking to evaluate the impact on the overall system.
• Contribute across disciplines to help the team achieve goals and deliverables.

Requirements

• Bachelor’s Degree in Engineering or equivalent education and experience.
• 10+ years of PCB and/or High-Density Package Layout design experience using industry-standard tools such as Cadence APD+.
• Proficiency with APD+ physical and electrical constraint editor.
• Experience with HDI stack-ups, including blind and buried microvias, RF dielectric materials, and trace widths/spacings from approximately 15 μm down to 2 μm or smaller.
• Experience with 2.5D devices, interposer or substrate design, flip-chip, surface mount, die stacking, package stacking, and substrate stacking techniques.
• Experience using a Cadence schematic/netlist-driven CAD layout process (APD+/Allegro) and supporting tools.
• High-end FPGA package or board design experience.
• Ability to collaborate with the Mechanical team to develop full 3D models for fit checks and thermal analysis.
• Understanding of layout techniques for digital, analog, and RF designs.
• Knowledge of electronic packaging techniques.
• Experience using a CAM package for manufacturing data validation; familiarity with CAM350 and Blueprint is preferred.
• Working knowledge of JEDEC/IPC design, fabrication, and assembly specifications.
• Experience creating assembly documentation and fabrication deliverables per company and industry standards.
• Must be a US Person.
• Ability to work effectively both independently and as part of a team.
• Commitment to teamwork, execution, and clear communication as part of the company culture.

Technologies

• Cadence APD+ (Allegro)
• APD+ physical and electrical constraint editor
• CAM 350
• Blueprint

Benefits

• Health care
• Dental
• Vision
• Life insurance
• 401(k)
• Education assistance
• Paid time off including PTO, holidays, and legally required paid leave

You will be a part of

You will join a team focused on the rapid development of affordable, chip-scale, secure, open system architecture devices. This cutting-edge capability supports the Department of Defense need for made-in-USA microelectronics that equip warfighters with state-of-the-art, trusted military-grade products built on leading commercial technologies.

To succeed in this role, you should have the following skills and experience

• Bachelor’s Degree in Engineering or equivalent education and experience.
• 10+ years of PCB and/or High-Density Package Layout design experience using Cadence APD+ or equivalent tools.
• Experience with APD+ physical and electrical constraint editor.
• HDI stack-ups including blind and buried microvias, RF dielectric materials, and fine trace widths/spacing down to 2 μm or smaller.
• Experience with 2.5D devices, interposer/substrate design, flip-chip, die stacking, and related techniques.
• Cadence schematic/netlist-driven CAD layout workflow experience.
• High-end FPGA packaging or board design experience.
• Ability to work with Mechanical teams to create 3D models for fit and thermal checks.
• Understanding of digital, analog, and RF layout techniques.
• Knowledge of electronic packaging techniques.
• Experience using CAM packages for manufacturing data validation; CAM350 and Blueprint familiarity preferred.
• Working knowledge of JEDEC/IPC design, fabrication, and assembly specifications.
• Experience producing assembly documentation and fabrication deliverables per standards.
• Must be a US Person.
• Ability to work well both independently and within a team, upholding teamwork, execution, and communication values.